1. Field of the Invention
The present invention relates to a data driving circuit and, more particularly, to a data driving circuit and a semiconductor memory device having the same which can generate a signal of various levels and amplitudes.
2. Description of the Related Art
A conventional data driving circuit includes a bias voltage generator which generates a bias voltage and a driver which receives a differential data signal to generate a differential output data signal. The driver includes a pre-driver and a main driver. The pre-driver and the main driver receive a differential input data signal and generate a differential output data signal by a current controlled by a bias voltage.
However, the conventional data driving circuit has a problem in that it is impossible to generate a differential output data signal having various levels and amplitudes desired at a receiving side.
FIG. 1 is a circuit diagram illustrating a conventional data driving circuit. The data driving circuit of FIG. 1 includes a main driver 10, pre-drivers 12-1 and 12-2, and a bias voltage generator 14. The main driver 10 includes resistors R1 and R2, NMOS transistors N1 and N2, and a current source I1. The pre-driver 12-1 includes a resistor R3, an NMOS transistor N3, and a current source I2, and the pre-driver 12-2 includes a resistor R4, an NMOS transistor N4, and a current source I3.
Operation of the data driving circuit of FIG. 1 is explained below.
The bias voltage generator 14 receives a bias voltage Vb to generate a bias voltage TVb. The current sources I1 to I3 are controlled by the bias voltage TVb to pass a constant current. The NMOS transistor N3 is turned on or off in response to an input data signal di, and the NMOS transistor N4 is turned on or off in response to an inverted input data signal diB. The pre-drivers 12-1 and 12-2 lower a voltage of a node a and raise a voltage of a node b when the differential input data signals di and diB have “high” and “low” levels, respectively. That is, at node a is a voltage generated by the resistor R3 and the current source I2 is subtracted from a voltage VDDQ, and at node b is a voltage VDDQ. On the other hand, when the differential input data signals di and diB are “low” level and “high” levels respectively, the pre-drivers 12-1 and 12-2 generate a voltage VDDQ at the node a and a voltage generated by the resistor R4 and the current source I3 is subtracted from a voltage VDDQ at the node b. The NMOS transistors N1 and N2 control a current flowing therethrough in response to voltages of the nodes a and b, respectively. That is, the main driver 10 generates differential output data signals do and doB of “high” level and “low” levels when node a is lower in voltage than node b, whereas the main driver 10 generates differential output data signals do and doB of “low” level and “high” levels when node b is lower in voltage than node a.
FIG. 2 is a detailed circuit diagram illustrating the data driving circuit of FIG. 1. The bias voltage generator 14 includes a resistor R5, NMOS transistors N9 and N10, and a comparator COM. The current source I1 includes NMOS transistors N5 and N6. The current source I2 includes an NMOS transistor N7. The current source I3 includes an NMOS transistor N8.
The NMOS transistors N7 and N8 are designed to be much wider in channel width than the NMOS transistors N5 and N6.
Operation of the data driving circuit of FIG. 2 is explained below.
The bias voltage generator 14 generates a constant bias voltage TVb such that it lowers bias voltage TVb when a voltage of a node c is higher than a bias voltage Vb and raises bias voltage TVb when the voltage of node c is lower than bias voltage Vb. The NMOS transistors N5 to N8 pass a constant current in response to bias voltage TVb. When bias voltage TVb is raised, an amount of a current passing through the NMOS transistors N5 to N8 is increased, whereas when bias voltage TVb is lowered, an amount of a current passing through the NMOS transistors N5 to N8 is decreased. When an amount of a current passing through the NMOS transistors N5 to N8 is increased, in response to the differential input data signals di and diB of “high” and “low” levels, the NMOS transistor N3 is turned on, and the NMOS transistor N4 is turned off. In this case, the voltage of node a becomes lower than it was before the bias voltage TVb was raised, and the voltage of node b becomes equal to what it was before bias voltage TVb was raised. Therefore, a resistance through the NMOS transistor N1 becomes greater than it was before bias voltage TVb was raised, and a resistance through the NMOS transistor N2 becomes equal to what it was before bias voltage TVb was raised. Consequently, a current flowing through the resistor R2 and the NMOS transistor N2 is increases more than a current flowing through the resistor R1 and the NMOS transistor N1. An output data signal do of a “high” level which is almost equal to what it was before a bias voltage TVb is raised and an output data doB which is lower than before a bias voltage TVb is raised are generated. On the other hand, when the differential input data signals di and diB of “low” and “high” levels are inputted, a level of the differential output data signals do and doB of “low” and “high” levels are generated. The differential output data signal do of a “low” level becomes lower than it was before a bias voltage TVb was raised. That is, as bias voltage TVb is raised, the differential output data signal of a “low” level becomes gradually lower, and thus an amplitude of the differential output data signals do and doB becomes gradually greater.
The conventional data driving circuit described above controls a current flowing through the main driver 10 and the pre-drivers 12-1 and 12-2 by the bias voltage TVb, thereby varying an amplitude and a level of the differential output data signals do and doB.
However, the conventional data driving circuit can vary an amplitude and a level of the differential output data signal by raising a bias voltage TVb but cannot shift a level.
Also, the conventional data driving circuit has a problem in that an increase of level of bias voltage TVb decreases a margin in saturation region of the NMOS transistors N5 to N8 of the pre-drivers 12-1 and 12-2 and the main driver 10, whereby the differential output data signals do and doB are sensitive to a noise.